The present invention relates to input and output interfaces for integrated circuits, and more particularly to high performance interfaces that have a high degree of flexibility and configurability.
Electronic systems are becoming more complex as they handle increasingly difficult tasks. Accordingly, the amount of data transferred between integrated circuits in these systems continues to climb. At the same time, system designers want smaller, lower pin-count packages that consume less space on the system""s printed circuit boards. Thus, very high data rates are desirable at integrated circuit input and output pins.
But it is also desirable for the circuits that form the input and output structures at these pins to be highly flexible. For example, sets, presets, and enables at registered inputs and outputs can ease the implementation of complicated logic functions, and JTAG boundary test access can simplify system diagnostics.
Unfortunately, increased flexibility results in slower circuits. The same transistors that add functions and increase multiplexing insert parasitic capacitances and resistances, slowing device performance. Increasing the configurability of an input and output interface decreases the maximum rate that the interface can process data. Also, to save power, integrated circuit designers want to use lower speed circuitry inside the integrated circuit.
Thus, what is needed is a highly flexible input and output interface that can also operate at high speed. For maximum utility, the interface should also be able to communicate efficiently with lower speed circuitry inside the integrated circuit.
Accordingly, embodiments of the present invention provide methods and apparatus for providing either high-speed, or lower-speed inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
One exemplary embodiment of the present invention provides an integrated circuit including a pad, a high-speed output buffer connected to the pad, and a low-speed output buffer also connected to the pad. The high-speed output buffer and the low-speed output buffer are selectably activated. When the high-speed output buffer is active, the low-speed output buffer is inactive, and when the low-speed output buffer is active, the high-speed output buffer is inactive.
This embodiment may further provide a first flip-flop connected to the high-speed output buffer, and a second flip-flop connected to the low-speed output buffer. The first flip-flop is configured to receive a first number of control signals and the second flip-flop is configured to receive a second number of control signals, the second number greater than the first number.
Another exemplary embodiment of the present invention provides an integrated circuit including a pad, a high-speed input buffer connected to the pad, and a low-speed input buffer also connected to the pad. The high-speed input buffer and the low-speed input buffer are selectably activated. When the high-speed input buffer is active, the low-speed input buffer is inactive, and when the low-speed input buffer is active, the high-speed input buffer is inactive.
This embodiment may further provide a first flip-flop connected to the high-speed input buffer, and a second flip-flop connected to the low-speed input buffer. The first flip-flop is configured to receive a first number of control signals and the second flip-flop is configured to receive a second number of control signals, the second number greater than the first number.
A further embodiment provides an integrated circuit including a high-speed output path. This path includes a first double-data rate register connected to a first output buffer. This integrated circuit also includes a low-speed output path having a second double-data register connected to a second output buffer, a high-speed input path having a third double-data rate register connected to a first input buffer, and a low-speed input path having a fourth double-data register connected to a second input buffer. The first output buffer, the second output buffer, the first input buffer, and the second input buffer are connected to a pad.
A better understanding of the nature and advantages of the present invention may be gained with reference to the following detailed description and the accompanying drawings.